This article is the 12th day article of ** Kochi University of Technology Advent Calendar 2015 **.
I really wanted to write about ROS, but I'm not motivated, so I'll write what I'm doing now.
Access Cyclone V's Lightweight HPS-to-FPGA Bridge with Python to read and write. In conclusion, I feel that it can be used as a test environment.
The board I'm using is Terasic's ** DE1-SoC **. BSP uses the official * Linux Ubuntu Desktop *. Python version is * 2.7.3 *
Altera's SoC FPGA has a convenient bus called * Lightweight HPS-to-FPGA Bridge *, so use that.
The contents that are mapped are written in Cyclone V HPS Memory Map, GPIO, UART, etc. It seems that you can also access the register of the peripheral of. Some self-made ips are mapped between ** 0xFF200000 ** and ** 0xFF3FFFFF **. (0x0 ~ 0x1FFFFF from the Qsys side)
This time, I will explain assuming that ip is connected from 0xFF200000 to 0xFF200010.
For now, import the required modules and open / dev / mem.
import os
import mmap
fd = os.open("/dev/mem",os.O_RDWR | os.O_SYNC)
#Area to use(Byte)
reg_span = 0x200000
# Lightweight HPS-to-FPGA Bridge offset
reg_base = 0xff200000
lw_h2f = mmap.mmap(fd ,reg_span ,mmap.MAP_SHARED,mmap.PROT_READ | mmap.PROT_WRITE,offset = reg_base)
You can now mmap the * Lightweight HPS-to-FPGA Bridge *. After that, move to the address you want to read and write and read and write.
lw_h2f.seek(0x0,os.SEEK_SET)
read_data1 = ord(lw_h2f.read_byte())
read_data2 = ord(lw_h2f.read_byte())
read_byte () is incremented arbitrarily. The increment interval was 1 byte in this environment. mmap.read_byte is read as a character string of length 1, so if you want to treat it as a number, you need to convert it with ** ord () **.
lw_h2f.seek(0x0,os.SEEK_SET)
write_byte(chr(write_data1))
write_byte(chr(write_data2))
This is also incremented without permission. The interval was 1 byte. As with reading, when writing, it must be written as a string of length 1, so it must be converted with ** chr () **.
I haven't written much about Python, but it wasn't difficult. I thought it would be an ant as an FPGA test environment. However, since the effective speed is fatally slow, it is not suitable for sharing SDRAM and exchanging a large amount of data (images, etc.). It seems that the correct answer is to treat the peripheral as a register.
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