Jupyter with PYNQ and high-level synthesis with Polyphony

Jupyter on a board called PYNQ

A board called PYNQ sold by Digilent can use Jupyter as standard. I will introduce it because it is a product with an interesting concept of cooperation with FPGA. Then, try using polyphony, a high-level synthesis tool that generates verilog from Python.

What is PYNQ?

For more information on PYNQ, please see here. It is a board equipped with an ARM + FPGA SoC called Zynq. I bought this kind of board in haste.

P in Pynq is P in Python. Make sure that the buttons are pink.

Don't you think it's interesting to have HDMI OUT / HDMI IN? Then, would you like to use it?

Power on + ready to use on the network

Normally, this kind of board has to be moved by looking at the manual and connecting various things, such as IoT or screaming in the middle of the night, but this board can be used quickly from daytime. If you turn on the power and connect to the network, you can easily connect to Windows by typing http: // pynq: 9090 in your browser. It seems that Samba and NetBIOS are working and resolving names for Windows.

Use sample face recognition (from USB camera)

You can easily use OpenCV face recognition by connecting a USB camera. Where's the FPGA? However, the feature is that it can be used without any equipment or preparation at hand. If you don't even have a USB camera, you can read from a file. If you have a video camera with HDMI output, you can also input from there. You are using FPGA for HDMI input.

The result is subtle, but I'm tired of capturing it, so forgive me. You can do it anyway.

Install and run Polyphony

Install a high-level synthesis tool called Polyphony. You should probably be able to do it with pip3 install. Here, I will break down what the high-level synthesis is and actually use it. The source to bite is the following Python code.

list11.py

from polyphony import testbench


def sum(l1:list):
    def sub_sum(l2:list):
        def sub_sub_sum(l2:list):
            s = 0
            for l in l2:
                s += l
            return s
        return sub_sub_sum(l2)
    return sub_sum(l1)

def list11(x):
    data1 = [x, 1, 2]
    data2 = [x, 1, 2, 3, 4, 5]
    s1 = sum(data1)
    s2 = sum(data2)
    return s1 + s2 + x

@testbench
def test():
    assert 18 == list11(0)
    assert 21 == list11(1)
    assert 24 == list11(2)


test()

It's a little sly, but I run it from Jupyter with subprocess.

Now you have polyphony_out.v.

This is the verilog code that was created !!

I would like to post all of them, but I have omitted it because it extends to 911 lines.

polyphony_out.v

module sum_sub_sum_sub_sub_sum
  (
    input wire signed [31:0] l21_q,
    input wire signed [12:0] l21_len,
    input wire CLK,
    input wire RST,
    input wire sub_sub_sum_READY,
    input wire sub_sub_sum_ACCEPT,
    output reg signed [31:0] sub_sub_sum_OUT0,
    output reg l21_req,
    output reg signed [31:0] l21_d,
    output reg signed [12:0] l21_addr,
    output reg l21_we,
    output reg sub_sub_sum_VALID  );

Zack's abbreviation

  begin
    if (in_addr[ADDR_WIDTH-1] == 1'b1) begin
      address = RAM_LENGTH + in_addr;
	end else begin
      address = in_addr;
    end
  end
  endfunction // address
  wire [ADDR_WIDTH-1:0] a;
  assign a = address(ADDR);
  assign Q = mem[read_addr];
  assign LEN = RAM_LENGTH;
  always @ (posedge CLK) begin
    if (WE)
      mem[ADDR] <= D;
	read_addr <= a;
  end
endmodule

What do you do after that?

You can probably simulate it by installing iverilog. I also have Samba, so I think that if done well, it can be synthesized in cooperation with Vivado. I haven't achieved that much yet.

It looks like it's about to be written, but that's it.