Decoder description in veriloggen (sample description of case statement)

I'm using a tool called veriloggen that can construct HDL (Hardware Description Language) descriptions using Python, but I had a hard time not knowing how to write a case statement like a decoder, so I'll leave it as a memo. I will.

decoder.py

from __future__ import absolute_import
from __future__ import print_function
import sys
import os
from veriloggen import *

def mkDecoder():

    m = Module('decoder')
    indata = m.Input('in', 3)
    out = m.OutputReg('out',8)

    decCond = []
    decCond.append( When(0)(out(0b00000001)) )
    decCond.append( When(1)(out(0b00000010)) )
    decCond.append( When(2)(out(0b00000100)) )
    decCond.append( When(3)(out(0b00001000)) )
    decCond.append( When(4)(out(0b00010000)) )
    decCond.append( When(5)(out(0b00100000)) )
    decCond.append( When(6)(out(0b01000000)) )
    decCond.append( When(7)(out(0b10000000)) )
    #decCond.append( When()(out(0b10000000)) )

    m.Always() (
        Case(indata)(
            *decCond
            )
        )

    return m

if __name__ == '__main__':
    dut = mkDecoder()
    verilog = dut.to_verilog(filename='dut.v')
    print(verilog)

    sim = simulation.Simulator(dut)
    rslt = sim.run()
    print(rslt)

"When (0) out (0b000000001)" means "when the value is 0, 00000001 is assigned to the variable (signal) out" in binary. Register the combination of such a value and the assignment expression in the list decCond. I commented it out this time, but you can add a default statement by using When () only at the end of this list. After that, the variable name used as input is specified in the Case statement in the always statement.