The SoC F1C100s on board has one USB OTG port. However, as of 09/13/2020, the [nano-5.2-tf branch] of LicheePi github (https://github.com/Lichee-Pi/linux/tree/nano-5.2-tf) cannot recognize the USB device.
Patch WhyCan Forum patched in the thread f1c100s linux 5.2 USB already complete driver, host + device complete driver Is open to the public. It seems that the patched source is placed in Baidu Wangpan, but it is unconfirmed because I do not have a Baidu account.
Below is a quote from diff
baseļ¼ 39402432e (grafted, HEAD -> nano-5.2-tf, origin/nano-5.2-tf) HEAD@{0}: clone: from https://github.com/Lichee-Pi/linux.git
diff:
modified: arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
modified: arch/arm/boot/dts/suniv-f1c100s.dtsi
modified: drivers/phy/allwinner/phy-sun4i-usb.c
modified: drivers/usb/musb/sunxi.c
diff --git a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
index ca644541a..890a57717 100644
--- a/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
+++ b/arch/arm/boot/dts/suniv-f1c100s-licheepi-nano.dts
@@ -20,7 +20,7 @@
};
panel: panel {
- compatible = "lg,lb070wv8", "simple-panel";
+ compatible = "qiaodian,qd43003c0-40", "simple-panel";
#address-cells = <1>;
#size-cells = <0>;
enable-gpios = <&pio 4 6 GPIO_ACTIVE_HIGH>;
@@ -79,3 +79,17 @@
pinctrl-0 = <&uart0_pe_pins>;
status = "okay";
};
+
+&otg_sram {
+ status = "okay";
+};
+
+&usb_otg {
+ dr_mode = "otg";
+ status = "okay";
+};
+
+&usbphy {
+ usb0_id_det-gpio = <&pio 4 2 GPIO_ACTIVE_HIGH>; /* PE2 */
+ status = "okay";
+};
diff --git a/arch/arm/boot/dts/suniv-f1c100s.dtsi b/arch/arm/boot/dts/suniv-f1c100s.dtsi
index 26d8e5577..437bdf7d9 100644
--- a/arch/arm/boot/dts/suniv-f1c100s.dtsi
+++ b/arch/arm/boot/dts/suniv-f1c100s.dtsi
@@ -221,6 +221,31 @@
resets = <&ccu RST_BUS_UART2>;
status = "disabled";
};
+ usb_otg: usb@1c13000 {
+ compatible = "allwinner,suniv-musb";
+ reg = <0x01c13000 0x0400>;
+ clocks = <&ccu CLK_BUS_OTG>;
+ resets = <&ccu RST_BUS_OTG>;
+ interrupts = <26>;
+ interrupt-names = "mc";
+ phys = <&usbphy 0>;
+ phy-names = "usb";
+ extcon = <&usbphy 0>;
+ allwinner,sram = <&otg_sram 1>;
+ status = "disabled";
+ };
+
+ usbphy: phy@1c13400 {
+ compatible = "allwinner,suniv-usb-phy";
+ reg = <0x01c13400 0x10>;
+ reg-names = "phy_ctrl";
+ clocks = <&ccu CLK_USB_PHY0>;
+ clock-names = "usb0_phy";
+ resets = <&ccu RST_USB_PHY0>;
+ reset-names = "usb0_reset";
+ #phy-cells = <1>;
+ status = "disabled";
+ };
fe0: display-frontend@1e00000 {
compatible = "allwinner,suniv-f1c100s-display-frontend";
reg = <0x01e00000 0x20000>;
diff --git a/drivers/phy/allwinner/phy-sun4i-usb.c b/drivers/phy/allwinner/phy-sun4i-usb.c
index 856927382..3cd9e946a 100644
--- a/drivers/phy/allwinner/phy-sun4i-usb.c
+++ b/drivers/phy/allwinner/phy-sun4i-usb.c
@@ -98,6 +98,7 @@
#define POLL_TIME msecs_to_jiffies(250)
enum sun4i_usb_phy_type {
+ suniv_phy,
sun4i_a10_phy,
sun6i_a31_phy,
sun8i_a33_phy,
@@ -859,6 +860,14 @@ static int sun4i_usb_phy_probe(struct platform_device *pdev)
return 0;
}
+static const struct sun4i_usb_phy_cfg suniv_cfg = {
+ .num_phys = 1,
+ .type = suniv_phy,
+ .disc_thresh = 3,
+ .phyctl_offset = REG_PHYCTL_A10,
+ .dedicated_clocks = true,
+};
+
static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
.num_phys = 3,
.type = sun4i_a10_phy,
@@ -973,6 +982,7 @@ static const struct sun4i_usb_phy_cfg sun50i_h6_cfg = {
};
static const struct of_device_id sun4i_usb_phy_of_match[] = {
+ { .compatible = "allwinner,suniv-usb-phy", .data = &suniv_cfg },
{ .compatible = "allwinner,sun4i-a10-usb-phy", .data = &sun4i_a10_cfg },
{ .compatible = "allwinner,sun5i-a13-usb-phy", .data = &sun5i_a13_cfg },
{ .compatible = "allwinner,sun6i-a31-usb-phy", .data = &sun6i_a31_cfg },
diff --git a/drivers/usb/musb/sunxi.c b/drivers/usb/musb/sunxi.c
index 832a41f9e..83f3fa5b0 100644
--- a/drivers/usb/musb/sunxi.c
+++ b/drivers/usb/musb/sunxi.c
@@ -714,14 +714,17 @@ static int sunxi_musb_probe(struct platform_device *pdev)
INIT_WORK(&glue->work, sunxi_musb_work);
glue->host_nb.notifier_call = sunxi_musb_host_notifier;
- if (of_device_is_compatible(np, "allwinner,sun4i-a10-musb"))
+ if (of_device_is_compatible(np, "allwinner,sun4i-a10-musb") ||
+ of_device_is_compatible(np, "allwinner,suniv-musb")) {
set_bit(SUNXI_MUSB_FL_HAS_SRAM, &glue->flags);
+ }
if (of_device_is_compatible(np, "allwinner,sun6i-a31-musb"))
set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags);
if (of_device_is_compatible(np, "allwinner,sun8i-a33-musb") ||
- of_device_is_compatible(np, "allwinner,sun8i-h3-musb")) {
+ of_device_is_compatible(np, "allwinner,sun8i-h3-musb") ||
+ of_device_is_compatible(np, "allwinner,suniv-musb")) {
set_bit(SUNXI_MUSB_FL_HAS_RESET, &glue->flags);
set_bit(SUNXI_MUSB_FL_NO_CONFIGDATA, &glue->flags);
}
@@ -812,6 +815,7 @@ static int sunxi_musb_remove(struct platform_device *pdev)
}
static const struct of_device_id sunxi_musb_match[] = {
+ { .compatible = "allwinner,suniv-musb", },
{ .compatible = "allwinner,sun4i-a10-musb", },
{ .compatible = "allwinner,sun6i-a31-musb", },
{ .compatible = "allwinner,sun8i-a33-musb", },
Modify and build the suniv-f1c100s-licheepi-nano.dts`` suniv-f1c100s.dtsi phy-sun4i-usb.c`` sunxi.c as described above to recognize the USB device. Become