Revive Frame Reader avec Quartus Prime 18.1
Aperçu
Si vous souhaitez afficher Linux Desktop à l'aide d'Intel SoC FPGA tel que DE10-nano, vous devez implémenter Frame Buffer du côté FPGA, mais comme le noyau IP du Frame Reader a été supprimé du récent Quartus Prime, J'ai dû utiliser une adresse IP payante. Cependant, la source du noyau IP de Frame Reader est restée dans Quartus Prime Lite / Standard 18.1 et peut être compilée avec Quartus Prime Lite 18.1.
procédure
(1) Recherchez le dossier *** frame_reader *** dans le dossier d'installation de Quartus Prime Lite 18.1. L'installation par défaut est sous *** C: \ intelFPGA_lite \ 18.1 \ ip \ altera ***.
(2) Copiez le dossier entier sous le projet Quartus que vous souhaitez compiler. S'il y a un dossier *** ip ***, il n'y a pas de problème en dessous.
(3) *** Il existe un fichier appelé ** alt_vip_vfr_hw.tcl ** dans *** <dossier copié> \ frame_reader \ full_ip \ frame_reader ***, alors remplacez tout le contenu de ce fichier par le code suivant.
(4) Ouvrez le projet Quartus, démarrez Platform Designer, et si ce qui suit est affiché dans le catalogue IP, c'est OK.
(5) Si Frame Reader est déjà installé sur le système, générez-le et recompilez-le tel quel, et le SOF de 18.1 sera terminé.
(6) Si le système n'implémente pas Frame Reader, vous pouvez ajouter Frame Reader et définir les paramètres. L'interface graphique est la même que l'ancien Frame Reader. (J'expliquerai comment implémenter Linux Desktop si nécessaire, mais je ne l'expliquerai pas en détail ici)
package require -exact qsys 18.1
#
# module alt_vip_vfr
#
set_module_property DESCRIPTION "The Frame Reader Megacore can be used to read a video stream from video frames stored a memory buffer"
set_module_property NAME alt_vip_vfr
set_module_property VERSION 18.1
set_module_property INTERNAL false
set_module_property OPAQUE_ADDRESS_MAP true
set_module_property GROUP test
set_module_property AUTHOR "Intel Corporation"
set_module_property DISPLAY_NAME "Frame Reader"
set_module_property DATASHEET_URL http://www.altera.com/literature/ug/ug_vip.pdf
set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
set_module_property EDITABLE true
set_module_property REPORT_TO_TALKBACK false
set_module_property ALLOW_GREYBOX_GENERATION false
set_module_property REPORT_HIERARCHY false
#
# file sets
#
add_fileset quartus_synth QUARTUS_SYNTH "" "Quartus Synthesis"
set_fileset_property quartus_synth TOP_LEVEL alt_vipvfr131_vfr
set_fileset_property quartus_synth ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property quartus_synth ENABLE_FILE_OVERWRITE_MODE true
add_fileset_file alt_vipvfr131_vfr.v VERILOG PATH src_hdl/alt_vipvfr131_vfr.v TOP_LEVEL_FILE
add_fileset_file alt_vipvfr131_vfr_controller.v VERILOG PATH src_hdl/alt_vipvfr131_vfr_controller.v
add_fileset_file alt_vipvfr131_vfr_control_packet_encoder.v VERILOG PATH src_hdl/alt_vipvfr131_vfr_control_packet_encoder.v
add_fileset_file alt_vipvfr131_prc.v VERILOG PATH src_hdl/alt_vipvfr131_prc.v
add_fileset_file alt_vipvfr131_prc_core.v VERILOG PATH src_hdl/alt_vipvfr131_prc_core.v
add_fileset_file alt_vipvfr131_prc_read_master.v VERILOG PATH src_hdl/alt_vipvfr131_prc_read_master.v
add_fileset_file alt_vipvfr131_common_package.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_package.vhd
add_fileset_file alt_vipvfr131_common_avalon_mm_bursting_master_fifo.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_avalon_mm_bursting_master_fifo.vhd
add_fileset_file alt_vipvfr131_common_avalon_mm_master.v VERILOG PATH ../../common_hdl/alt_vipvfr131_common_avalon_mm_master.v
add_fileset_file alt_vipvfr131_common_unpack_data.v VERILOG PATH ../../common_hdl/alt_vipvfr131_common_unpack_data.v
add_fileset_file alt_vipvfr131_common_avalon_mm_slave.v VERILOG PATH ../../common_hdl/alt_vipvfr131_common_avalon_mm_slave.v
add_fileset_file alt_vipvfr131_common_stream_output.v VERILOG PATH ../../common_hdl/alt_vipvfr131_common_stream_output.v
add_fileset_file alt_vipvfr131_common_pulling_width_adapter.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_pulling_width_adapter.vhd
add_fileset_file alt_vipvfr131_common_general_fifo.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_general_fifo.vhd
add_fileset_file alt_vipvfr131_common_fifo_usedw_calculator.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_fifo_usedw_calculator.vhd
add_fileset_file alt_vipvfr131_common_gray_clock_crosser.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_gray_clock_crosser.vhd
add_fileset_file alt_vipvfr131_common_std_logic_vector_delay.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_std_logic_vector_delay.vhd
add_fileset_file alt_vipvfr131_common_one_bit_delay.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_one_bit_delay.vhd
add_fileset_file alt_vipvfr131_common_logic_fifo.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_logic_fifo.vhd
add_fileset_file alt_vipvfr131_common_ram_fifo.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_ram_fifo.vhd
add_fileset_file alt_vipvfr131_vfr.sdc SDC PATH alt_vipvfr131_vfr.sdc
add_fileset sim_verilog SIM_VERILOG "" "Verilog Simulation"
set_fileset_property sim_verilog TOP_LEVEL alt_vipvfr131_vfr
set_fileset_property sim_verilog ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property sim_verilog ENABLE_FILE_OVERWRITE_MODE true
add_fileset_file alt_vipvfr131_vfr.v VERILOG PATH src_hdl/alt_vipvfr131_vfr.v
add_fileset_file alt_vipvfr131_vfr_controller.v VERILOG PATH src_hdl/alt_vipvfr131_vfr_controller.v
add_fileset_file alt_vipvfr131_vfr_control_packet_encoder.v VERILOG PATH src_hdl/alt_vipvfr131_vfr_control_packet_encoder.v
add_fileset_file alt_vipvfr131_prc.v VERILOG PATH src_hdl/alt_vipvfr131_prc.v
add_fileset_file alt_vipvfr131_prc_core.v VERILOG PATH src_hdl/alt_vipvfr131_prc_core.v
add_fileset_file alt_vipvfr131_prc_read_master.v VERILOG PATH src_hdl/alt_vipvfr131_prc_read_master.v
add_fileset_file alt_vipvfr131_common_package.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_package.vhd
add_fileset_file alt_vipvfr131_common_avalon_mm_bursting_master_fifo.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_avalon_mm_bursting_master_fifo.vhd
add_fileset_file alt_vipvfr131_common_avalon_mm_master.v VERILOG PATH ../../common_hdl/alt_vipvfr131_common_avalon_mm_master.v
add_fileset_file alt_vipvfr131_common_unpack_data.v VERILOG PATH ../../common_hdl/alt_vipvfr131_common_unpack_data.v
add_fileset_file alt_vipvfr131_common_avalon_mm_slave.v VERILOG PATH ../../common_hdl/alt_vipvfr131_common_avalon_mm_slave.v
add_fileset_file alt_vipvfr131_common_stream_output.v VERILOG PATH ../../common_hdl/alt_vipvfr131_common_stream_output.v
add_fileset_file alt_vipvfr131_common_pulling_width_adapter.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_pulling_width_adapter.vhd
add_fileset_file alt_vipvfr131_common_general_fifo.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_general_fifo.vhd
add_fileset_file alt_vipvfr131_common_fifo_usedw_calculator.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_fifo_usedw_calculator.vhd
add_fileset_file alt_vipvfr131_common_gray_clock_crosser.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_gray_clock_crosser.vhd
add_fileset_file alt_vipvfr131_common_std_logic_vector_delay.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_std_logic_vector_delay.vhd
add_fileset_file alt_vipvfr131_common_one_bit_delay.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_one_bit_delay.vhd
add_fileset_file alt_vipvfr131_common_logic_fifo.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_logic_fifo.vhd
add_fileset_file alt_vipvfr131_common_ram_fifo.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_ram_fifo.vhd
add_fileset_file alt_vipvfr131_vfr.sdc SDC PATH alt_vipvfr131_vfr.sdc
add_fileset sim_vhdl SIM_VHDL "" "VHDL Simulation"
set_fileset_property sim_vhdl TOP_LEVEL alt_vipvfr131_vfr
set_fileset_property sim_vhdl ENABLE_RELATIVE_INCLUDE_PATHS false
set_fileset_property sim_vhdl ENABLE_FILE_OVERWRITE_MODE true
add_fileset_file alt_vipvfr131_vfr.v VERILOG PATH src_hdl/alt_vipvfr131_vfr.v
add_fileset_file alt_vipvfr131_vfr_controller.v VERILOG PATH src_hdl/alt_vipvfr131_vfr_controller.v
add_fileset_file alt_vipvfr131_vfr_control_packet_encoder.v VERILOG PATH src_hdl/alt_vipvfr131_vfr_control_packet_encoder.v
add_fileset_file alt_vipvfr131_prc.v VERILOG PATH src_hdl/alt_vipvfr131_prc.v
add_fileset_file alt_vipvfr131_prc_core.v VERILOG PATH src_hdl/alt_vipvfr131_prc_core.v
add_fileset_file alt_vipvfr131_prc_read_master.v VERILOG PATH src_hdl/alt_vipvfr131_prc_read_master.v
add_fileset_file alt_vipvfr131_common_package.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_package.vhd
add_fileset_file alt_vipvfr131_common_avalon_mm_bursting_master_fifo.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_avalon_mm_bursting_master_fifo.vhd
add_fileset_file alt_vipvfr131_common_avalon_mm_master.v VERILOG PATH ../../common_hdl/alt_vipvfr131_common_avalon_mm_master.v
add_fileset_file alt_vipvfr131_common_unpack_data.v VERILOG PATH ../../common_hdl/alt_vipvfr131_common_unpack_data.v
add_fileset_file alt_vipvfr131_common_avalon_mm_slave.v VERILOG PATH ../../common_hdl/alt_vipvfr131_common_avalon_mm_slave.v
add_fileset_file alt_vipvfr131_common_stream_output.v VERILOG PATH ../../common_hdl/alt_vipvfr131_common_stream_output.v
add_fileset_file alt_vipvfr131_common_pulling_width_adapter.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_pulling_width_adapter.vhd
add_fileset_file alt_vipvfr131_common_general_fifo.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_general_fifo.vhd
add_fileset_file alt_vipvfr131_common_fifo_usedw_calculator.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_fifo_usedw_calculator.vhd
add_fileset_file alt_vipvfr131_common_gray_clock_crosser.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_gray_clock_crosser.vhd
add_fileset_file alt_vipvfr131_common_std_logic_vector_delay.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_std_logic_vector_delay.vhd
add_fileset_file alt_vipvfr131_common_one_bit_delay.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_one_bit_delay.vhd
add_fileset_file alt_vipvfr131_common_logic_fifo.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_logic_fifo.vhd
add_fileset_file alt_vipvfr131_common_ram_fifo.vhd VHDL PATH ../../common_hdl/alt_vipvfr131_common_ram_fifo.vhd
#
# documentation links
#
add_documentation_link "Data Sheet" http://www.altera.com/literature/ug/ug_vip.pdf
add_documentation_link "Data Sheet" http://www.altera.com/literature/ug/ug_vip.pdf
#
# parameters
#
add_parameter FAMILY STRING "Cyclone IV" "Current device family selected"
set_parameter_property FAMILY DEFAULT_VALUE "Cyclone IV"
set_parameter_property FAMILY DISPLAY_NAME "Device family selected"
set_parameter_property FAMILY TYPE STRING
set_parameter_property FAMILY VISIBLE false
set_parameter_property FAMILY UNITS None
set_parameter_property FAMILY DESCRIPTION "Current device family selected"
set_parameter_property FAMILY AFFECTS_GENERATION false
set_parameter_property FAMILY SYSTEM_INFO_TYPE DEVICE_FAMILY
add_parameter BITS_PER_PIXEL_PER_COLOR_PLANE INTEGER 8 "The number of bits used per pixel, per color plane"
set_parameter_property BITS_PER_PIXEL_PER_COLOR_PLANE DEFAULT_VALUE 8
set_parameter_property BITS_PER_PIXEL_PER_COLOR_PLANE DISPLAY_NAME "Bits per pixel per color plane"
set_parameter_property BITS_PER_PIXEL_PER_COLOR_PLANE TYPE INTEGER
set_parameter_property BITS_PER_PIXEL_PER_COLOR_PLANE UNITS None
set_parameter_property BITS_PER_PIXEL_PER_COLOR_PLANE ALLOWED_RANGES 4:16
set_parameter_property BITS_PER_PIXEL_PER_COLOR_PLANE DESCRIPTION "The number of bits used per pixel, per color plane"
set_parameter_property BITS_PER_PIXEL_PER_COLOR_PLANE AFFECTS_GENERATION false
set_parameter_property BITS_PER_PIXEL_PER_COLOR_PLANE HDL_PARAMETER true
add_parameter NUMBER_OF_CHANNELS_IN_PARALLEL INTEGER 3 "The number color planes transmitted in parallel"
set_parameter_property NUMBER_OF_CHANNELS_IN_PARALLEL DEFAULT_VALUE 3
set_parameter_property NUMBER_OF_CHANNELS_IN_PARALLEL DISPLAY_NAME "Number of color planes in parallel"
set_parameter_property NUMBER_OF_CHANNELS_IN_PARALLEL TYPE INTEGER
set_parameter_property NUMBER_OF_CHANNELS_IN_PARALLEL UNITS None
set_parameter_property NUMBER_OF_CHANNELS_IN_PARALLEL ALLOWED_RANGES 1:4
set_parameter_property NUMBER_OF_CHANNELS_IN_PARALLEL DESCRIPTION "The number color planes transmitted in parallel"
set_parameter_property NUMBER_OF_CHANNELS_IN_PARALLEL AFFECTS_GENERATION false
set_parameter_property NUMBER_OF_CHANNELS_IN_PARALLEL HDL_PARAMETER true
add_parameter NUMBER_OF_CHANNELS_IN_SEQUENCE INTEGER 1 "The number color planes transmitted in sequence"
set_parameter_property NUMBER_OF_CHANNELS_IN_SEQUENCE DEFAULT_VALUE 1
set_parameter_property NUMBER_OF_CHANNELS_IN_SEQUENCE DISPLAY_NAME "Number of color planes in sequence"
set_parameter_property NUMBER_OF_CHANNELS_IN_SEQUENCE TYPE INTEGER
set_parameter_property NUMBER_OF_CHANNELS_IN_SEQUENCE UNITS None
set_parameter_property NUMBER_OF_CHANNELS_IN_SEQUENCE ALLOWED_RANGES 1:3
set_parameter_property NUMBER_OF_CHANNELS_IN_SEQUENCE DESCRIPTION "The number color planes transmitted in sequence"
set_parameter_property NUMBER_OF_CHANNELS_IN_SEQUENCE AFFECTS_GENERATION false
set_parameter_property NUMBER_OF_CHANNELS_IN_SEQUENCE HDL_PARAMETER true
add_parameter MAX_IMAGE_WIDTH INTEGER 640 "The maximum width of images / video frames"
set_parameter_property MAX_IMAGE_WIDTH DEFAULT_VALUE 640
set_parameter_property MAX_IMAGE_WIDTH DISPLAY_NAME "Maximum Image width"
set_parameter_property MAX_IMAGE_WIDTH TYPE INTEGER
set_parameter_property MAX_IMAGE_WIDTH UNITS None
set_parameter_property MAX_IMAGE_WIDTH ALLOWED_RANGES 32:2600
set_parameter_property MAX_IMAGE_WIDTH DESCRIPTION "The maximum width of images / video frames"
set_parameter_property MAX_IMAGE_WIDTH AFFECTS_GENERATION false
set_parameter_property MAX_IMAGE_WIDTH HDL_PARAMETER true
add_parameter MAX_IMAGE_HEIGHT INTEGER 480 "The maximum height of images / video frames"
set_parameter_property MAX_IMAGE_HEIGHT DEFAULT_VALUE 480
set_parameter_property MAX_IMAGE_HEIGHT DISPLAY_NAME "Maximum Image height"
set_parameter_property MAX_IMAGE_HEIGHT TYPE INTEGER
set_parameter_property MAX_IMAGE_HEIGHT UNITS None
set_parameter_property MAX_IMAGE_HEIGHT ALLOWED_RANGES 32:2600
set_parameter_property MAX_IMAGE_HEIGHT DESCRIPTION "The maximum height of images / video frames"
set_parameter_property MAX_IMAGE_HEIGHT AFFECTS_GENERATION false
set_parameter_property MAX_IMAGE_HEIGHT HDL_PARAMETER true
add_parameter MEM_PORT_WIDTH INTEGER 256 "The width in bits of the master port"
set_parameter_property MEM_PORT_WIDTH DEFAULT_VALUE 256
set_parameter_property MEM_PORT_WIDTH DISPLAY_NAME "Master port width"
set_parameter_property MEM_PORT_WIDTH TYPE INTEGER
set_parameter_property MEM_PORT_WIDTH UNITS None
set_parameter_property MEM_PORT_WIDTH ALLOWED_RANGES 16:256
set_parameter_property MEM_PORT_WIDTH DESCRIPTION "The width in bits of the master port"
set_parameter_property MEM_PORT_WIDTH AFFECTS_GENERATION false
set_parameter_property MEM_PORT_WIDTH HDL_PARAMETER true
add_parameter RMASTER_FIFO_DEPTH INTEGER 64 "The depth of the read master FIFO"
set_parameter_property RMASTER_FIFO_DEPTH DEFAULT_VALUE 64
set_parameter_property RMASTER_FIFO_DEPTH DISPLAY_NAME "Read master FIFO depth"
set_parameter_property RMASTER_FIFO_DEPTH TYPE INTEGER
set_parameter_property RMASTER_FIFO_DEPTH UNITS None
set_parameter_property RMASTER_FIFO_DEPTH ALLOWED_RANGES 8:1024
set_parameter_property RMASTER_FIFO_DEPTH DESCRIPTION "The depth of the read master FIFO"
set_parameter_property RMASTER_FIFO_DEPTH AFFECTS_GENERATION false
set_parameter_property RMASTER_FIFO_DEPTH HDL_PARAMETER true
add_parameter RMASTER_BURST_TARGET INTEGER 32 "The target burst size of the read master"
set_parameter_property RMASTER_BURST_TARGET DEFAULT_VALUE 32
set_parameter_property RMASTER_BURST_TARGET DISPLAY_NAME "Read master FIFO burst target"
set_parameter_property RMASTER_BURST_TARGET TYPE INTEGER
set_parameter_property RMASTER_BURST_TARGET UNITS None
set_parameter_property RMASTER_BURST_TARGET ALLOWED_RANGES 2:256
set_parameter_property RMASTER_BURST_TARGET DESCRIPTION "The target burst size of the read master"
set_parameter_property RMASTER_BURST_TARGET AFFECTS_GENERATION false
set_parameter_property RMASTER_BURST_TARGET HDL_PARAMETER true
add_parameter CLOCKS_ARE_SEPARATE INTEGER 1 "Use separate clock for the Avalon-MM master interface"
set_parameter_property CLOCKS_ARE_SEPARATE DEFAULT_VALUE 1
set_parameter_property CLOCKS_ARE_SEPARATE DISPLAY_NAME "Use separate clock for the Avalon-MM master interface"
set_parameter_property CLOCKS_ARE_SEPARATE TYPE INTEGER
set_parameter_property CLOCKS_ARE_SEPARATE UNITS None
set_parameter_property CLOCKS_ARE_SEPARATE ALLOWED_RANGES 0:1
set_parameter_property CLOCKS_ARE_SEPARATE DESCRIPTION "Use separate clock for the Avalon-MM master interface"
set_parameter_property CLOCKS_ARE_SEPARATE DISPLAY_HINT boolean
set_parameter_property CLOCKS_ARE_SEPARATE AFFECTS_GENERATION false
set_parameter_property CLOCKS_ARE_SEPARATE HDL_PARAMETER true
#
# display items
#
#
# connection point clock_reset
#
add_interface clock_reset clock end
set_interface_property clock_reset clockRate 0
set_interface_property clock_reset ENABLED true
set_interface_property clock_reset EXPORT_OF ""
set_interface_property clock_reset PORT_NAME_MAP ""
set_interface_property clock_reset CMSIS_SVD_VARIABLES ""
set_interface_property clock_reset SVD_ADDRESS_GROUP ""
add_interface_port clock_reset clock clk Input 1
#
# connection point clock_reset_reset
#
add_interface clock_reset_reset reset end
set_interface_property clock_reset_reset associatedClock clock_reset
set_interface_property clock_reset_reset synchronousEdges DEASSERT
set_interface_property clock_reset_reset ENABLED true
set_interface_property clock_reset_reset EXPORT_OF ""
set_interface_property clock_reset_reset PORT_NAME_MAP ""
set_interface_property clock_reset_reset CMSIS_SVD_VARIABLES ""
set_interface_property clock_reset_reset SVD_ADDRESS_GROUP ""
add_interface_port clock_reset_reset reset reset Input 1
#
# connection point clock_master
#
add_interface clock_master clock end
set_interface_property clock_master clockRate 0
set_interface_property clock_master ENABLED true
set_interface_property clock_master EXPORT_OF ""
set_interface_property clock_master PORT_NAME_MAP ""
set_interface_property clock_master CMSIS_SVD_VARIABLES ""
set_interface_property clock_master SVD_ADDRESS_GROUP ""
add_interface_port clock_master master_clock clk Input 1
#
# connection point clock_master_reset
#
add_interface clock_master_reset reset end
set_interface_property clock_master_reset associatedClock clock_master
set_interface_property clock_master_reset synchronousEdges DEASSERT
set_interface_property clock_master_reset ENABLED true
set_interface_property clock_master_reset EXPORT_OF ""
set_interface_property clock_master_reset PORT_NAME_MAP ""
set_interface_property clock_master_reset CMSIS_SVD_VARIABLES ""
set_interface_property clock_master_reset SVD_ADDRESS_GROUP ""
add_interface_port clock_master_reset master_reset reset Input 1
#
# connection point avalon_slave
#
add_interface avalon_slave avalon end
set_interface_property avalon_slave addressAlignment NATIVE
set_interface_property avalon_slave addressUnits WORDS
set_interface_property avalon_slave associatedClock clock_reset
set_interface_property avalon_slave associatedReset clock_reset_reset
set_interface_property avalon_slave bitsPerSymbol 8
set_interface_property avalon_slave burstOnBurstBoundariesOnly false
set_interface_property avalon_slave burstcountUnits WORDS
set_interface_property avalon_slave explicitAddressSpan 0
set_interface_property avalon_slave holdTime 0
set_interface_property avalon_slave linewrapBursts false
set_interface_property avalon_slave maximumPendingReadTransactions 0
set_interface_property avalon_slave maximumPendingWriteTransactions 0
set_interface_property avalon_slave readLatency 1
set_interface_property avalon_slave readWaitStates 0
set_interface_property avalon_slave readWaitTime 0
set_interface_property avalon_slave setupTime 0
set_interface_property avalon_slave timingUnits Cycles
set_interface_property avalon_slave writeWaitTime 0
set_interface_property avalon_slave ENABLED true
set_interface_property avalon_slave EXPORT_OF ""
set_interface_property avalon_slave PORT_NAME_MAP ""
set_interface_property avalon_slave CMSIS_SVD_VARIABLES ""
set_interface_property avalon_slave SVD_ADDRESS_GROUP ""
add_interface_port avalon_slave slave_address address Input 5
add_interface_port avalon_slave slave_write write Input 1
add_interface_port avalon_slave slave_writedata writedata Input 32
add_interface_port avalon_slave slave_read read Input 1
add_interface_port avalon_slave slave_readdata readdata Output 32
set_interface_assignment avalon_slave embeddedsw.configuration.isFlash 0
set_interface_assignment avalon_slave embeddedsw.configuration.isMemoryDevice 0
set_interface_assignment avalon_slave embeddedsw.configuration.isNonVolatileStorage 0
set_interface_assignment avalon_slave embeddedsw.configuration.isPrintableDevice 0
#
# connection point interrupt_sender
#
add_interface interrupt_sender interrupt end
set_interface_property interrupt_sender associatedAddressablePoint avalon_slave
set_interface_property interrupt_sender associatedClock clock_reset
set_interface_property interrupt_sender associatedReset clock_reset_reset
set_interface_property interrupt_sender bridgedReceiverOffset ""
set_interface_property interrupt_sender bridgesToReceiver ""
set_interface_property interrupt_sender ENABLED true
set_interface_property interrupt_sender EXPORT_OF ""
set_interface_property interrupt_sender PORT_NAME_MAP ""
set_interface_property interrupt_sender CMSIS_SVD_VARIABLES ""
set_interface_property interrupt_sender SVD_ADDRESS_GROUP ""
add_interface_port interrupt_sender slave_irq irq Output 1
# -- Dynamic Ports (elaboration callback) --
set_module_property ELABORATION_CALLBACK vfr_elaboration_callback
proc vfr_elaboration_callback {} {
# +-----------------------------------
# | connection point avalon_streaming_source
# |
set color_planes_in_parallel [get_parameter_value NUMBER_OF_CHANNELS_IN_PARALLEL]
set bps [get_parameter_value BITS_PER_PIXEL_PER_COLOR_PLANE]
set data_width [expr $bps * $color_planes_in_parallel]
add_interface avalon_streaming_source avalon_streaming start
set_interface_property avalon_streaming_source dataBitsPerSymbol $bps
set_interface_property avalon_streaming_source symbolsPerBeat $color_planes_in_parallel
set_interface_property avalon_streaming_source errorDescriptor ""
set_interface_property avalon_streaming_source maxChannel 0
set_interface_property avalon_streaming_source readyLatency 1
add_interface_port avalon_streaming_source dout_data data Output $data_width
add_interface_port avalon_streaming_source dout_valid valid Output 1
add_interface_port avalon_streaming_source dout_ready ready Input 1
add_interface_port avalon_streaming_source dout_startofpacket startofpacket Output 1
add_interface_port avalon_streaming_source dout_endofpacket endofpacket Output 1
set_interface_property avalon_streaming_source ASSOCIATED_CLOCK clock_reset
set_interface_property avalon_streaming_source ENABLED true
# |
# +-----------------------------------
# +-----------------------------------
# | connection point avalon_master
# |
set mem_port_width [get_parameter_value MEM_PORT_WIDTH]
add_interface avalon_master avalon start
set_interface_property avalon_master burstOnBurstBoundariesOnly false
set_interface_property avalon_master doStreamReads false
set_interface_property avalon_master doStreamWrites false
set_interface_property avalon_master linewrapBursts false
set_interface_property avalon_master ASSOCIATED_CLOCK clock_master
set_interface_property avalon_master ENABLED true
set burst_target [get_parameter_value RMASTER_BURST_TARGET]
add_interface_port avalon_master master_address address Output 32
add_interface_port avalon_master master_burstcount burstcount Output [expr int(ceil((log($burst_target + 1))/(log(2))))]
add_interface_port avalon_master master_readdata readdata Input $mem_port_width
add_interface_port avalon_master master_read read Output 1
add_interface_port avalon_master master_readdatavalid readdatavalid Input 1
add_interface_port avalon_master master_waitrequest waitrequest Input 1
# |
# +-----------------------------------
}
** Comment avez-vous fait cela? ** **
L'original ** alt_vip_vfr_hw.tcl ** était un tcl de l'époque de SOPC Builder, il ne peut donc pas être lu par Platform Designer tel quel. Bien sûr, il est également possible d'analyser tcl à partir de zéro et de l'écrire pour Platform Designer. Mais c'est un peu pénible. Par conséquent, je l'ai converti par la procédure suivante.
(1) Installez Quartus II 13.1 sur votre ordinateur. C'est à peu près à cette époque que SOPC Builder a été basculé sur Qsys, il y avait donc une fonction pour lire le tcl de SOPC Builder avec Qsys également.
(2) Si vous ouvrez le noyau avec l'éditeur de composants de Qsys et le fermez, il sera converti en tcl de Qsys. À ce stade, vous devez faire attention à ce que l'éditeur de composants indique que le code d'exécution (dans le code ci-dessus, la partie ci-dessous "# --Dynamic Ports (élaboration callback) -") est inclus dans le tcl. Puisqu'il ne peut pas être ouvert, il est nécessaire de supprimer le code exécutable de tcl puis de l'ouvrir.
(3) Restaurez la partie du code d'exécution converti de tcl et enregistrez-la.
Vous disposez désormais d'un noyau IP qui peut également être ouvert dans Platform Designer. Cependant, je ne sais pas si tout fonctionne de cette façon, et même si cela semble fonctionner sur Platform Designer, je ne sais pas si le noyau implémenté fonctionnera de manière fiable, alors faites-le à vos risques et périls. ..