In the middle of proceeding with the introductory book of C (no progress)

It feels like how many times I've been introduced, but I'm doing this

[Introduction to C language-From basic knowledge to the essence of computers](https://www.amazon.co.jp/C%E8%A8%80%E8%AA%9E%E6%9C%AC%E6%A0 % BC% E5% 85% A5% E9% 96% 80-% E5% 9F% BA% E7% A4% 8E% E7% 9F% A5% E8% AD% 98% E3% 81% 8B% E3% 82% 89% E3% 82% B3% E3% 83% B3% E3% 83% 94% E3% 83% A5% E3% 83% BC% E3% 82% BF% E3% 81% AE% E6% 9C% AC% E8% B3% AA% E3% 81% BE% E3% 81% A7-% E7% A8% AE% E7% 94% B0-% E5% 85% 83% E6% A8% B9 / dp / 4774196169)

make……？makefile? It's not just a compilation like a common introductory book in the street, but a makefile is created and compiled, so it's a form close to practice. (It seems to be)

I was ignorant

Even though I had actually compiled with make, I read on and thought, "I just changed the name of the executable file, so I don't need to bother to make a Makefile?" When I muttered on Twitter, there was a thankful tsukkomi saying useful for big projects with hundreds and thousands of source files.

It's quite embarrassing that I should have been indebted to make in the field so far (although it's about half a year), but I didn't know how to write it or what kind of merit it has.

How to write a Makefile

`Makefile.hoge`


PROGRAM = hoge
OBJS    = hoge.o
SRCS    = $(OBJS:%.o=%.c)
CC      = gcc
CFLAGS  = -g -Wall
LDFLAGS =

$(PROGRAM):$(OBJS)
     $(CC) $(CFLAGS) $(LDFLAGS) -o $(PROGRAM) $(OBJS) $(LDLIBS)

There is a tab after CC in the PROGRAM line. I will explain what it means from above. PROGRAM: Program name, which is the name of the executable file OBJS: List the object file names to be linked, separated by spaces. You can specify multiple files by writing them in succession like hoge.o fuga.o ... Do you recognize that? SRCS: Specify the file name of the source code. Here, the extension of OBJS is set to .c so that the compilation target is hoge.c. CC: C compiler command name. Here gcc CFLAGS: Compile option specification. Here we specify -g for the debugger and -Wall for stricter warnings. LDFLAGS: Linker option specification (I'm not sure, so I'll omit it. It seems to be used when linking special libraries etc.) $ (PROGRAM): Description of how to generate a program

There seem to be other ways to write a Makefile, so I still need to study ...

Build using Makefile

$ make -f Makefile.hoge

The build process looks like this

gcc -g -Wall -c -o hoge.o hoge.c
gcc -g -Wall -o hoge hoge.o

Now that the executable file hoge is created, it can be executed as follows.

$ ./hoge

Summary

・ Makefile is convenient for large-scale development ・ Various writing styles

…… But make There are many ways to write it, but even if you google it, the book is [O'Reilly book](https://www.amazon.co.jp/GNU-Make-%E7%AC%AC3%E7%89% 88-Robert-Mecklenburg / dp / 4873112699 / ref = asc_df_4873112699 /? Tag = jpgo-22 & linkCode = df0 & hvadid = 295678107984 & hvpos = 1o2 & hvnetw = g & hvrand = 26528690058319140 & hvpone = & hvptwo = & hvqmt = & hvptwo = & hvqmt = -523848454026 & psc = 1 & th = 1 & psc = 1) What does it mean to only come out? Is it wrong to find out?

Let's make a Makefile and build it (super beginner)